4合1多工器

system_clk #200 clk1(a);
system_clk #100 clk2(b);
system_clk #50 clk3(c);
system_clk #25 clk4(d);
all n1(f,a,b,c,d);
endmodule



module all(f,a,b,c,d);
input a,b,c,d;
output f;
wire a1,b1,c1,d1,x,y,z,k;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(x,a1,b1,c);
and(y,b,c,d1);
and(z,a,c,d);
and(k,a,b1,c1,d1);
or(f,x,y,z,k);
endmodule



module system_clk(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(PERIOD-1)$stop;
endmodule

4_in_1

module top;
system_clk #200 clk1(a);
system_clk #100 clk2(b);
system_clk #50 clk3(c);
system_clk #25 clk4(d);
4_in_1 n1(f,a,b,c,d);
endmodule

module 4_in_1(f,a,b,c,d);
input a,b,c,d;
output f;
wire a1,b1,c1,d1,x,y,z,k;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(x,a1,b1,c);
and(y,a1,d);
and(z,b,c1,d);
and(k,a,c,d1);
or(f,x,y,z,k);
endmodule

module system_clk(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(PERIOD-1)$stop;
endmodule

and not

module top;
reg A,B;
wire D;
nand_f n1(C,A,B);
not_f n1(D,C);

initial begin
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;
#2 A=1'b0;
#10$finish;
end
endmodule


module nand_f(C,A,B);
input A,B;
output C;
nand(C,A,B);
specify
specparam
tpd_0_1=3.0:3.0:3.0,
tpd_1_0=3.0:3.0:3.0;
(A=>C)=(tpd_0_1,tpd_1_0);
(B=>C)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module not_f(D,C);
input C;
output D;
not(D,C);
specify
specparam
tpd_0_1=2.0:2.0:2.0,
tpd_1_0=2.0:2.0:2.0;
(C=>D)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

反向傳遞延遲

module top;
wire o,a1;

system_clk #100 clk2(a1);
nanf201 c1 (o,a1);
endmodule

module nanf201(o,a1);
input a1;
output o;
not(o,a1);
specify
specparam
tpd_0_1=1.13:3.09:7.75,
tpd_1_0=0.93:2.5:7.34;
(a1=>o)=(tpd_0_1,tpd_1_0);
endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

[3:0]

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule
module and4_algo(y_out,x_in);

input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always @(x_in)
begin :and_loop
y_out=1;
for (k=0;k<=3;k=k+1)
if (x_in[k] == 0)
begin
y_out = 0;
disable and_loop;
end
end
endmodule
module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

4in1

module top;
wire x_in1,x_in2,x_in3,x_in4;

system_clk #400 clk1(x_in1);
system_clk #200 clk2(x_in2);
system_clk #100 clk3(x_in3);
system_clk #50 clk4(x_in4);
and4_rtl c1(x_in1,x_in2,x_in3,x_in4,y_out);
endmodule


module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

05