4in1

module top;
wire x_in1,x_in2,x_in3,x_in4;

system_clk #400 clk1(x_in1);
system_clk #200 clk2(x_in2);
system_clk #100 clk3(x_in3);
system_clk #50 clk4(x_in4);
and4_rtl c1(x_in1,x_in2,x_in3,x_in4,y_out);
endmodule


module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule